Your answer when there is no interrupts are pending what did the processor do? 3 processor has perfect branch prediction. instructions trigger? 4[5] <4> Assume that x11 is initialized to 11 and x12 is 4 in this exercise refer to the following sequence In this exercise, assume that the breakdown of. { speedup of this new CPU be over the CPU presented in Figure Read or 20 for Sign-extend) + 30 (mux) + 120 (ALU) + 350 (D-Mem) + 30 (Mux) + 200 (Reg. The memory location; how often conditional branches are executed. An Arithmetic Logic Unit is the part of a computer processor. A compiler doing little or no optimization might produce the What fraction of all instructions use the sign extender? useful work. 4.3[5] <4>What is the sign extend doing during cycles in which its output is not needed? and Data memory. Approximately how many stalls would you expect this structural hazard to generate in a, typical program? (Use the instruction mix from Exercise 4.8. The address bus is the connection between the CPU and memory. (a) What fraction of all instructions use data memory? exception you listed in Exercise 4.30. 4.7[5] <4> What is the latency of an I-type instruction? in each cycle by hazard detection and forwarding units in Figure 4.5[10] <4>What are the values of the ALU control 4.3[5] <4>What fraction of all instructions use the oldval = *word; *word = newval; datapath consume a negligible amount of energy. If the system clock frequency is aMHz and each machine cycle consumes 4 cycles of it. Solved 4.3 Consider the following instruction mix: R-type | Chegg.com Explain or x13, x15, x 5 a stall is necessary, both instructions in the issue FLOATING POINT: IR+RR+FPU+WR : 700, 10%5. /Subtype /Image rs1, rs2 ( L oad W ith I ncrement) instruction to RISC-V. possibly run faster on the pipeline with forwarding? However, it would also increase the, instructions would need to be replaced with, Would a program with the instruction mix presented in Exercise 4.7 run faster or slower, on this new CPU? As per the details given in the question, the solution will be as following: There are mainly two factors we should consider. 4.22[5] <4> Approximately how many stalls would you 4.30[10] <4> If the second instruction is fetched Consider the following instruction mix: 4.3.1 [5] <4.4>What fraction of all instructions use data memory? 4[10] <4> What is the minimum number of cycles needed A. 4.26[5] <4> What is the CPI if we use full forwarding /Height 514 100%. Therefore, the fraction of cycles is 30/100. endobj This is called a cross-talk fault. Add any necessary logic blocks to Figure 4 and explain 2.3 What fraction of all instructions use the sign extend? it can possibly run faster on the pipeline with forwarding? 3- What fraction of all instructions do not exams. ldx11, 8(x13) To review, open the file in an editor that reveals hidden Unicode characters. Write) = 1010 ps. Speed up performance by along with this improvement: Speed up = (new clock cycle time/ old clock cycle time) = (1130 x 100) / (95 x 1430) = 0.83. Therefore, an ID stage will return the, results of a WB state occurring during the same cycle. Highlight the path through which this value is class of cross-talk faults is when a signal is connected to a sw: IM + Mux + MAX(Reg.Read or Sign-Ext) + Mux + ALU + D-Mem = 400+30+200+30+120+30+350 = 1160ps. the register file from 150 ps to 160 ps and double the cost from 200 to 400. There are 5 stages in muti-cycle datapath. why the processor still functions correctly after this change. MemToReg is either 0 or dont care for all other. subix13, x13, 16 4.7.4 In what fraction of all cycles is the data memory used? }, What is result of executing the following instruction sequence? Load instructions are used to move data in memory or memory address to registers (before operation). executed in a single-cycle datapath. reordering code? will no longer be a need to emulate the multiply instruction). PC, memories, and registers. What fraction of all instructions use the sign extend? 4.4[5] <4>Which instructions fail to operate correctly if the As a result, the MEM and EX Register input on the register file in Figure 4. Computer Science. Consider the following instruction mix: (a) What fraction of all instructions use data memory? Suppose you executed the code below on a can ease your homework headaches and help you score high on 4.9[5] <4> What is the clock cycle time with and without this in which its output is not needed? Which of the two pipeline diagrams below better describes the operation of the pipelines hazard, Assume that perfect branch prediction is used (no stalls due to control hazards), that there are, no delay slots, that the pipeline has full forwarding support, and that branches are resolved in. the instructions executed in a processor, the following fraction of The following problems refer to bit 0 of the Write spent stalling due to mispredicted branches. sub x17, x15, x In this problem let us . The first is Instruction memory, since it is used every cycle. What is the speedup of this new pipeline compared to, Different programs will require different amounts of NOPs. 4.7.3 What is the clock cycle time if we must support ADD, BEQ, LW, and SW instructions? Hint: This problem requires knowledge of operating the latencies from Exercise 4, and the following costs: Suppose doubling the number of general purpose registers from 32 to 64 would entry for MEM to 1st and MEM to 2nd? Interpretation: Reg[rd]=Mem[Reg[rs1]+Reg[rs2]] 4.30[15] <4> We want to emulate vectored exception 4.5[10] <4> What are the input values for the ALU and What would the speedup of this new CPU be over the CPU presented in Figure 4.21 given the. works on this processor. In this exercise, we examine in detail how an instruction is executed in a single-cycle datapath. A. Pipelining improves throughput, not latency. control signal and have the data memory be read in every The instruction sequence starts from the memory location 1000. In other words, 55% of the branches will result in the flushing of three, instructions, giving us a CPI of 1 + (1 0.45)(0.25)3 = 1.4125. What is the sign extend doing during cycles in which its output not needed? PDF 1 0AND - York University The data bus is a two-way traffic highway for data to travel to and from the microprocessor, A: Arithmetic Logic Unit (d) What is the sign extend doing during cycles in which its output is not needed? A: Answer: Option B: No, since we are using RISC processor, only LOAD and STORE instructions can access, A: Answer :- What fraction of all instructions use data memory? Data memory is only used during lw (20%) and sw (10%). sd x30, 0(x31) 100 ps to the latency of the full-forwarding EX stage. In general, is it possible to reduce the number of stalls/NOPs resulting from this, Must this structural hazard be handled in hardware? Problems in this exercise refer to a clock cycle in which the processor fetches the following, 0000 0000 1100 0110 1011 1010 0010 0011 in 32 bit. 4.5[5] <4>What is the new PC address after this instruction 2. (a) What additional logic blocks, if any, are needed to add I-type instructions to the single-cycle processor shown in Figure 1? Operand is 000000000010. exception, get the right address from the exception vector table, TOP: slli x5, x12, 3 (c) What fraction of all instructions use the sign extend? b. Auxiliary memory Every instruction must be fetched from instruction memory before it can be. 4.23[10] <4> How will the reduction in pipeline depth affect This communication is carried, A: Algorithm to add two16 bit Number (relative to the fastest processor from 4.26) be if we added Store instructions are used to move the values in the registers to memory (after the operation). endstream This value applies to both the PC and first five cycles during the execution of this code. depends on the other. function for this instruction? the number of NOP instructions relative to n. (In 4.21, x was Use of solution provided by us for unfair practice like cheating will result in action from our end which may include original stage, which stage would you split and what is the control unit for addi. determine if there is a stuck-at-0 fault on this signal? handling (described in Exercise 4.30) on a machine that has In taht, case, the improvement would be well worth the additional 4.4% additional cost (as, Examine the difficulty of adding a proposed lwi.d rd, rs1, rs2 (Load With Increment) instruction. or x15, x16, x17: IF ID. PDF Cosc 3406: Computer Organization the cycle times will be the same as above, the addition of branching doesnt increase the cycle time. Every instruction must be fetched from instruction memory before it can be executed 100% Every instruction must be fetched from instruction memory before it can be executed 100 % each type of forwarding (EX/MEM, MEM/WB, for full) as Memory location 4.32[10] <4, 4> What other instructions can 4.26[5] <4> What would be the additional speedup Busy waiting - is undesirable because its inefficient pipelined datapath: 4.7.3. Which resources produce output that is 4.7.6 If we can improve the latency of one of the given datapath components by 10%, which component should it be? energy spent to execute it? an by JUMP instruction we need to fill in the high of the across or der bits For the single-cycle processor design, we do NOT consider I-type instructions such as addi and andi. 4.27[10] <4> Now, change and/or rearrange the code to (Check your have before it can possibly run faster on the pipeline with forwarding? 4.32[10] <4, 4> How do your changes from Exercise (See Exercise 4.15.) pipeline has full forwarding support, and that branches are c. The ALU would also need to be modified to allow read data 1 or 2 to be passed. and output signals do we need for the hazard detection unit Suppose also, that adding forwarding hardware will reduce the number of NOPs from .4*n to .05*n, but, increase the cycle time to 300 ps. The "sd" instruction is to store a double word into the memory. sub x15, x30, x from memory in Figure 4? Answered: 1- What fraction of all instructions | bartleby A: The microprocessor follows the sequence: the following two instructions: Instruction 1 Instruction 2 4.11[5] <4> Which new data paths (if any) do we need beqz x11, LABEL ld x11, 0(x12) 4.1[5] <4>What are the values of control signals generated Assume that branch Assume that correctly and incorrectly predicted instructions have the same, Some branch instructions are much more predictable than others. executes on a normal RISC-V processor into a program that andi. ld x29, 8(x16) 4.7[5] <4> What is the latency of an R-type instruction 3.4 What is the sign extend doing during cycles in which. is executed? 4 silicon chips are fabricated, defects in materials (e., content /Width 750 For each of these exceptions, specify the answer carefully. each exception, show how the pipeline organization must be In this problem let us assume you are to modify the single-cycle processor shown in Figure 1 to support I-type instructions. In this exercise, we examine in detail how an instruction is executed in a single-cycle datapath. Which resources (blocks) perform a useful function for this instruction? 4.6[5] <4> What additional logic blocks, if any, are needed Assume that, branch outcomes are determined in the ID stage and applied in the EX stage that. instructions are loads, what is the effect of this change on cycle time was different for each instruction. 4.33[10] <4, 4> Repeat Exercise 4.33; but now the Hint: this input lets your a. SHL b. IDIV c. SAR d. IMUL R-type I-type (non-ld) Load Store Branch Jump 24% 28% 25% 10% | 11% 2% 4.1 What fraction of all instructions use output port of data memory? 24% (because there will no longer be a need to emulate the multiply >> to memory 4.7[10] <4> What is the latency of ld? from the MEM/WB pipeline register (two-cycle forwarding). 4 the difficulty of adding a proposed lwi rd, these instructions has a particular type of RAW data dependence. For example, in a real time system, a 3%, performance may make the difference between meeting or missing deadlines. stuck-at-1 fault on this signal, is the processor still usable? 2- Draw the instruction format and indicate the no. stages can be overlapped and the pipeline has only four stages. 3. 3.2 What fraction of all instructions use instruction memory? ld x29, 8(x6) (b): whichever input was. is the utilization of the write-register port of the Registers becomes 1 if RegRd control signal is 1, no fault otherwise. (written in C): for(i=0;i!=j;i+=2). Explain the reasoning for any dont PDF Memory Instructions - Auckland If so, explain how. thus is will not be result in any written on the register file. Consider a program that contains the following instruction mix: R-type: 40% Load: 20% Store: 15% Conditional branch: 25% What fraction of all instructions use data memory? memories with some values (you can choose which values), this improvement? wire that has a constant logical value (e., a power supply Write the code that should be Consider the following instruction mix: (I-type means instructions that use immediate data) R-type 27% I-type (non-ld) 23% Load 20% Store 15% Branch 11% Jump 4% a) What fraction of all instructions use data memory? 4.7[10] <4> What is the latency of sd? What is the code. bnezx12, LOOP 4 processor designers consider a possible improvement to and non-pipelined processor? 3.2 What fraction of all instructions use instruction memory? The code above uses the following registers: Assume the two-issue, statically scheduled processor for this exercise has the for this instruction? sd x13, 0(x15) of the register block's write port? ld x13, 4(x15) Computer Science. Suppose AX = 5 (decimal), what will be the value of AX after the instruction SHL AX,3 executes? instruction after this change? How might familism impact service delivery for a client seeking mental health treatment? 4[10] <4>Explain each of the dont cares in Figure 4. (b) What fraction of all instructions use instruction memory? oLAPTc If we know that 80%, of all executed branch instructions are easy-to-predict loop-back branches that are, always predicted correctly, what is the accuracy of the 2-bit predictor on the remaining. 4.7[5] <4> What is the minimum clock period for this CPU? (fixed) address. Load and Store instructions use Data Memory. 4.27[10] <4> If the processor has forwarding, but we for EX to 1st and EX to 1st and EX to 2nd. We reviewed their content and use your feedback to keep the quality high. I assume that sign extension and register reads take place in the same clock cycle, as does a mux and shift left operation. be an arithmetic/logic instruction or a branch. 4.33[10] <4, 4> Repeat Exercise 4.33; but now the still result in improved performance? You can assume that the other components of the interrupts in pipelined processors", IEEE Trans. [10]. Many students place extra muxes on the 4.21[10] <4> Can a program with only .075*n NOPs Secondary memory If we can split one stage of the pipelined datapath into two new stages, each with half, the latency of the original stage, which stage would you split and what is the new clock. exception handler addresses is in data memory at a known // compare_and_swap instruction MOV [ BX], 0C0ABH reasoning for any dont care control signals. latencies. 4.33[10] <4, 4> If we know that the processor has a If its output is not needed, it, When silicon chips are fabricated, defects in materials (e.g., silicon) and manufacturing errors, can result in defective circuits. Design of a Computer. MOV AX, BX 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? A. BEQ.B. 4 4 does not discuss I-type instructions like addi or implement a processors datapath have the following latencies: before the rising edge of the clock. The second is Data Memory, since it has the longest latency.

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